a) Field of the Invention
The present invention relates to a semiconductor device and its manufacture method, and more particularly to a semiconductor device with dynamic random access memories (DRAMs) and its manufacture method.
b) Description of the Related Art
DRAMs are widely used as storage devices. The application fields of DRAMs are expanding to portable electronic apparatuses, and there is a great need for low power consumption of DRAMs. The capacity of a battery housed in a portable electronic apparatus is limited so that the less the storage device consumes power, the better.
It is necessary for a DRAM to rewrite its data at a predetermined time interval. The memory cell of a DRAM generally has one transistor and one capacitor. Electric charges stored in the capacitor indicate the contents of stored data. One electrode of the capacitor is connected to one electrode (storage node) of the transistor, and the stored charges gradually reduce because of leak current from the storage node.
In order to recover the reduced, stored charges, the data is required to be rewritten. This data rewrite operation is called a refresh operation. If the refresh period is short, the power consumption becomes large. In order to reduce this power consumption, it is efficient to prolong the period of the refresh operation. To this end, it is desired to improve the data retention characteristics (refresh characteristics) of a storage node.
The refresh characteristics are deteriorated by junction leak current flowing out of a diffusion layer which forms part of the storage node of the memory cell, and dominantly affected by defects caused by contamination during the manufacture processes or other reasons. There are many presumable reasons but they are not still definitely decided to be actual reasons.
According to a report of IEDM95 (1995), pp. 915-918, a retention (holding) time of DRAM is largely dependent upon the impurity concentration of a well in which the DRAM cell is formed, and the higher the well impurity concentration, the worse the refresh characteristics. This report analyzes that as the well concentration is raised, thermal ion field emission (TFE) current increases and forms a tail distribution of the retention time.
Techniques of forming DRAMs by using a retrograde triple well has been proposed (for example, U.S. Pat. No. 5,404,042 and JP-A 8-97378, which are incorporated herein by reference). The triple well is a combination of a double well, and complementary single or simple wells. The double well of the triple well structure is also called a triple well, implying that it is accompanied with a simple well of the same conductivity type. A retrograde well is a well having a maximum impurity concentration at a deep position in the well.
If a memory cell is implemented in a retrograde well formed as the inner well of the double well constituting the triple well, the memory cell becomes very resistant to a-ray soft errors. The manufacture process of a retrograde well, using high energy ion implantation, is simple and manufacture cost can be lowered. In addition, resistance to latch-up is excellent in a retrograde well.
FIGS. 10A-10E are cross sectional views illustrating a conventional method of manufacturing DRAMs using the retrograde well.
As shown in FIG. 10A, the surface of a p-type silicon substrate 101 is oxidized to grow a silicon oxide film (buffer film) 130 to a thickness of 3 nm. A silicon nitride film 131 is deposited 115 nm thick on the silicon oxide film 130 by CVD. The silicon nitride film 131 is patterned through photolithography using a resist mask.
Thereafter, a photoresist mask 123b is formed which has openings in the areas corresponding to n-type wells to be next formed. Phosphorous ions are implanted at an acceleration energy of 180 keV and at a dose of 1.4xc3x971013 cmxe2x88x922 to form n-type regions 102a and 102b. After the photoresist mask 123b is removed, the substrate is subjected to heat treatment for 90 minutes at 1150xc2x0 C. to form deep n-type wells 102a and 102b. 
As shown in FIG. 10B, by using the patterned silicon nitride film 131 as a mask, wet oxidation is performed at 1100xc2x0 C. to selectively grow field oxide films 125 of 350 nm thickness on the silicon substrate. Thereafter, the silicon nitride film 131 and silicon oxide buffer film 130 are removed. Dry oxidation is performed at 900xc2x0 C. to grow silicon oxide films (not shown) of 10 nm thickness in the areas where the field oxide films 125 are not formed.
As shown in FIG. 10C, a photoresist mask 123c is formed. This photoresist mask 123c has openings which expose a partial area of the exposed surface of the p-type silicon substrate 101 and a partial area of the n-type well 102b. Boron ions are implanted to form p-type regions 104 and 103. Ion implantation is performed three times, at an acceleration energy of 180 keV and a dose of 1.5xc3x971013 cmxe2x88x922, at an acceleration energy of 100 keV and a dose of 2xc3x971012 cmxe2x88x922, and at an acceleration energy of 50 keV and a dose of 1xc3x971012 cmxe2x88x922, respectively.
The ion implantation at the acceleration energy of 180 keV forms a retrograde portion having a high impurity concentration at a bottom portion of the well. The next ion implantation at the acceleration energy of 100 keV sets the threshold value Vt of a parasitic field transistor under the field oxide film 125 higher than a certain value to form a so-called channel stop region. The ion implantation at the acceleration energy of 50 keV interconnects a p-type region finally formed by ion implantation for adjusting a threshold value of n-channel MOS transistors to be formed later and the p-type region formed at the acceleration energy of 100 keV.
Thereafter, the photoresist mask 123c is removed. After the photoresist mask 123c is removed, boron ions are implanted over the whole surface of the substrate at an acceleration energy of 18 keV and a dose of 2xc3x971012 cmxe2x88x922. This ion implantation sets desired threshold values of p-channel MOS transistors to be formed in the n-type wells 102a and 102b and n-channel MOS transistors to be formed in the p-type well 104 and in a peripheral circuit region 103a in the p-type triple well 103.
As shown in FIG. 10D, a photoresist mask 123d is formed over the semiconductor substrate surface. This photoresist mask 123d has an opening which exposes a memory cell region 103b of the p-type triple well 103. By using the photoresist mask 123d as a mask, boron ions are implanted at an acceleration energy of 18 keV and a dose of 3xc3x971012 cmxe2x88x922. This ion implantation sets the threshold value Vt of a transfer transistor to be formed in the memory cell region 103b higher than that of a transistor to be formed in the peripheral circuit region 103a. Thereafter, the photoresist mask 123d is removed.
After the photoresist mask 123d is removed, the oxide film of 10 nm thickness formed before the ion implantation processes is removed, and the semiconductor substrate is processed in a dry oxidizing atmosphere at 900xc2x0 C. to grow a gate oxide film of 10 nm thickness.
FIG. 10E is a schematic diagram showing the triple well structure formed as above. The n-type well 102a and p-type well 104 are used for forming p-channel MOS transistors and n-channel MOS transistors of a peripheral circuit.
The exposed region of the n-type well 102b and the p-type well region 103a in the n-type well 102b are used for forming a CMOS sense amplifier circuit. The p-type well region 103b in the n-type well 102b is used for forming memory cells.
With the ion implantation processes described above, the threshold values of MOS transistors to be formed in respective regions can be regulated or adjusted to desired values. Thereafter, an insulated gate electrode (word line), a source/drain region (bit line), a capacitor, and the like are formed by usual manufacture processes.
The above-described manufacture method has four mask processes in total up to forming the gate oxide film.
DRAMs having an excellent performance can be manufactured by incorporating the triple well structure having a retrograde well. However, it has been found not satisfactory in that a DRAM circuit is associated with other problems if the refresh characteristics are intended to be improved further.
It is an object of the present invention to provide a semiconductor device having improved refresh characteristics without degrading other characteristics.
It is another object of the present invention to provide a DRAM semiconductor device having memory cells and peripheral circuits excellent in performance.
It is a further object of the present invention to provide a method of efficiently manufacturing such a semiconductor device.
According to one aspect of the present invention, there is provided a semiconductor device comprising: a semiconductor substrate having one surface; a first well and a second well respectively formed in a first region and a second region in areas of the one surface of the semiconductor substrate, the first and second wells each having a local maximum of a first conductivity type impurity concentration at a depth position apart from the one surface of the semiconductor substrate, and one of a depth and the first conductivity type impurity concentration of the local maximum of the second well is larger than that of the first well, and the other is at least equal to that of the first well; a memory cell formed in the first well; and a peripheral circuit for the memory cell formed in the second well.
According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of: defining a memory cell area and a peripheral circuit area on a surface of a semiconductor substrate; forming a first well by implanting first conductivity type impurity ions into the memory cell area a plurality of times and at different acceleration energies, the first well having a first local maximum of a first conductivity type impurity concentration at a first depth position; and forming a second well by implanting first conductivity type impurity ions into the peripheral circuit area a plurality of times and at different acceleration energies, the second well having a second local maximum of the first conductivity type impurity concentration at a second depth position, wherein one of the second depth position and the second local maximum is larger than a corresponding one of the first depth position and the first local maximum, and the other is at least equal to a corresponding one of the first depth position and the first local maximum.
The impurity concentration distributions of a plurality of retrograde wells of the same conductivity type are set differently to provide characteristics suitable for each retrograde well. For the retrograde well in which a memory cell is formed, the impurity concentration distribution is set so that the refresh characteristics are improved. In contrast to the memory cell, transistors in the peripheral circuit area which are applied with high voltage can be made to have a high breakdown voltage and the characteristics of the transistors are prevented from being deteriorated.
Transistors having different characteristics can be efficiently formed in triple well structures having a retrograde well.
The refresh characteristics of a DRAM memory cell can be improved and a breakdown voltage and the like of each transistor in the peripheral circuit can be properly preserved.